1. Field of the Invention
The present invention relates to apparatuses and methods for locking a phase of an output signal, and more particularly to a phase locking method and a phase locked loop (PLL) that includes a self-biased voltage-current converter.
2. Description of the Related Art
A phase locked loop (PLL) capable of outputting a stable oscillating output having a frequency that is equal to a frequency of a reference signal or a frequency generated by dividing/multiplying the frequency of the reference signal is used in various ways. As examples, the PLL is widely used to generate various frequencies for an application specific integrated circuit (ASIC), a system on chip (SoC), and so on. Generally, a PLL includes a divider in a feedback path where a division ratio of the divider or a multiplication factor is a value of M. The PLL can generate a clock signal that has a relatively high frequency based on a reference signal that has a relatively low frequency, and can generate a clock signal that has a desired frequency by controlling the division ratio.
However, when using the divider, a frequency band and/or jitter characteristics of the PLL can vary according to the division ratio, and can be sensitive to process, voltage, and temperature (PVT) variations.
As the PLL is widely used in portable devices, requirements for reducing a size and a power consumption of the PLL become very important. Thus, PVT variations that affect the frequency band and/or the jitter characteristics should be considered weighty.
FIG. 1 is a block diagram illustrating a conventional PLL. Referring to FIG. 1, the PLL 10 includes a phase frequency detector (PFD) 11, a charge pump 12, a loop filter 13, a voltage controlled oscillating (VCO) 14, and a main divider 15.
The PLL 10 receives a reference signal φref having a reference frequency, and generates an output signal φout of which a frequency is M times the reference frequency of the reference signal φref. The PFD 11 detects a phase difference between the reference signal φref and the output signal φout, generates an up signal or a down signal, and provides the up signal or the down signal to the charge pump 12. The charge pump 12 provides a predetermined current to the loop filter 13 according to the up signal or the down signal. The loop filter 13 receives the predetermined current, generates a control voltage to be supplied to the VCO 14, and maintains the voltage at a constant level. The VCO 14 receives the control voltage, and generates the output signal φout, of which the frequency is proportional to the control voltage. The main divider 15 receives the output signal φout, and generates a frequency-divided output signal, of which the frequency is 1/M times the frequency of the output signal φout. The frequency-divided output signal is applied to the PFD 11. As described above, the PLL 10 can generate the output signal φout, of which the frequency is maintained substantially constant.
A transfer function G1(s) of the PLL 10 is obtained as shown in Expression 1 below:
                                                                        G                ⁢                                                                  ⁢                1                ⁢                                  (                  s                  )                                            =                                                Φ                  ⁢                                                                          ⁢                  out                                                  Φ                  ⁢                                                                          ⁢                  ref                                                                                                        =                                                                                          Icp                      ⁢                                                                                                                                  2                      ⁢                                                                                          ⁢                      π                                                        ·                                      H                    ⁡                                          (                      s                      )                                                        ·                                      Kvco                    s                                                                    1                  +                                                            Icp                                              2                        ⁢                                                                                                  ⁢                        π                                                              ·                                          H                      ⁡                                              (                        s                        )                                                              ·                                          Kvco                      s                                        ·                                          1                      M                                                                                                                                              =                                                                                          Icp                      ·                      Kvco                                                              2                      ⁢                                                                                          ⁢                                              π                        ·                        Clp                                                                              ·                                      (                                          1                      +                                              s                        ·                        Rlp                        ·                        Clp                                                              )                                                                                                              s                      .                                        2                                    +                                                                                    Icp                        ·                        Kvco                        ·                        Rlp                                                                    2                        ⁢                                                                                                  ⁢                                                  π                          ·                          M                                                                                      ·                    s                                    +                                                            Icp                      ·                      Kvco                                                              2                      ⁢                                                                                          ⁢                                              π                        ·                        M                        ·                        Clp                                                                                                                                                    [                  Expression          ⁢                                          ⁢          1                ]                                          H          ⁡                      (            s            )                          ≈                              1            +                          s              ·              Rlp              ·              Clp                                            s            ·            Clp                                                          
where Icp indicates a pump current provided from the charge pump 12, H(s) indicates an approximate function of a transfer function of the loop filter 13, Kvco indicates a proportional constant of the VCO 14, Clp indicates a capacitance of the loop filter 13, Rlp indicates a resistance of the loop filter 13, φref indicates a phase of a reference signal, and φout indicates a phase of an output signal.
A bandwidth Δω of the PLL 10 is obtained as shown in Expression 2 below, which is taken from a denominator of the transfer function G1(s) in Expression 1.
                              Δ          ⁢                                          ⁢          w                =                              Icp            ·            Kvco            ·            Rlp                                2            ⁢                                                  ⁢                          π              ·              M                                                          [                  Expression          ⁢                                          ⁢          2                ]            
Referring to Expression 2, the bandwidth Δω depends upon the pump current Icp provided from the charge pump 12, the resistance Rlp of the loop filter 13, the proportional constant Kvco of the VCO 14, and the division ratio M of the main divider 15. Thus, the PLL 10 is sensitive to PVT variations.
In addition, the loop filter in the PLL includes a large capacitor and a resistor. Generally, when a circuit is formed in a semiconductor chip, a capacitor occupies a large area in the semiconductor chip. If the resistance in the loop filter is increased to reduce a size of the capacitor in the loop filter, while maintaining the characteristic of the loop filter, the bandwidth of the PLL is also increased, as shown in Expression 2. If the pump current provided from the charge pump is reduced to reduce the size of the capacitor in the loop filter, while maintaining the bandwidth of the PLL, the characteristics of the PLL actually become difficult to preserve. In other words, reducing the size of the capacitor is not easy, and as a result, reducing the size of the PLL is difficult.